High input impedance and low output impedance are characteristic of an emitter follower circuit. Also, because it has a large current gain, it is widely utilized as a buffer circuit for driving a capacitive load.
FIG. 9 and FIG. 10 show examples of configurations of widely-used emitter follower circuits.
The emitter follower circuit shown in FIG. 9 has npn transistor Q101 and resistor R101.
The npn transistor Q101 is connected to supply voltage line VCC by its collector, and its emitter is connected to ground line G via resistor R101. In addition, the output voltage of amplification circuit AMP101 of the previous stage is input to its base.
In the case of the emitter follower circuit shown in FIG. 9, the base of npn transistor Q101 is used as input, and the emitter of npn transistor Q101 is used as output.
When the potential of the output becomes lower than the potential of the input, and the potential difference becomes greater than the forward voltage of the pn junction, the emitter current of npn transistor Q101 increases suddenly, and a current flows from the emitter to the load (series circuit comprising capacitor CL and resistor RL in the case of the example shown in FIG. 9). When the difference between the potentials of the output and the input becomes smaller than the forward voltage of the pn junction as capacitor CL of the load is charged by said current, the emitter current of npn transistor Q101 decreases to stop the output of current to the load.
In addition, if the output acquires a higher potential than the input, npn transistor Q101 turns off to pull a current into resistor R101 from the load. When the potential of the output becomes lower than that of the input to the extent that the forward voltage of the pn junction as the electric charge in capacitor CL is discharged by said pulled-in current, the emitter current of npn transistor Q101 charges capacitor CL in the aforementioned manner to restrain the output voltage from dropping.
As such, a voltage obtained by shifting the input voltage by the forward voltage of the pn junction is constantly generated at the output of the emitter follower circuit. Therefore, the gain with respect to an AC voltage signal is almost “1,” and the output signal becomes in-phase with the input signal.
The emitter follower circuit shown in FIG. 10 is provided with npn transistor Q102 in addition to a configuration (npn transistor Q101 and resistor R101) similar to that of the emitter follower circuit shown in FIG. 9.
The npn transistor Q102 is inserted between the emitter of npn transistor Q101 and resistor R101, and a prescribed bias voltage is supplied to its base by bias supply circuit B101.
The npn transistor Q102 is a constant current circuit for letting prescribed bias current lbs flow between the emitter of npn transistor Q101 and ground line G. A current can be pulled in from the load as long as said bias current lbs is not exceeded.
The emitter follower circuits shown in FIG. 9 and FIG. 10 are problematic in that their capability for sending out current from supply voltage line VCC to the load is lower than their capacity to pull a current into ground line G from the load. That is, while a large current can be supplied through npn transistor Q101 when the current is to be sent out to the load, the level of the current is restricted by the constant current circuit, for example, when the current is to be pulled in from the load. Because the speed of capacitor discharge is restricted when the pulled-in current is restricted, the output current fails to follow changes in the input voltage when the capacitor has a large capacitance or when the signal frequency is high, and the waveform ends up being distorted.
FIG. 11 consists of graphs showing example output voltage waveforms of conventional emitter follower circuits. The signal frequency is approximately 500 kHz in FIG. 11 (A), and it is approximately 50 MHz in FIG. 11 (B). As can be understood by looking at the part surrounded by the dotted line in FIG. 11 (B), when the frequency is increased from 500 kHz to 50 MHz, the output voltage begins to fail to follow changes in the input voltage during the period in which current is pulled in from the load, and the waveform ends up being distorted.
In order to correct said distortion of the output waveform, bias current lbs, applied between the emitter of npn transistor Q101 and ground line G, should be increased. However, if bias current lbs is increased, bias current lbs flows at all times regardless of the presence of the load, resulting in the problem of increased power consumption.
The present invention was created in light of such situation, and its objective is to present a buffer circuit by which the load can be driven at high speed while restraining an increase in power consumption.